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課程名稱 |
計算機結構
COMPUTER ARCHITECTURE |
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開課學期 |
98-2 |
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授課對象 |
電機資訊學院 電機工程學系 |
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授課教師 |
吳安宇 |
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課號 |
EE4039 |
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課程識別碼 |
901 43200 |
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班次 |
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學分 |
3 |
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全/半年 |
半年 |
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必/選修 |
選修 |
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上課時間 |
星期五2,3,4(9:10~12:10) |
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上課地點 |
電二225 |
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備註 |
總人數上限：60人 |
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課程簡介影片 |
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核心能力關聯 |
核心能力與課程規劃關聯圖 |
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課程大綱
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為確保您我的權利,請尊重智慧財產權及不得非法影印
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課程概述 |
CHAPTER 1 COMPUTER ABSTRACTIONS AND TECHNOLOGY
CHAPTER 2 INSTRUCTIONS: LANGUAGE OF THE COMPUTER
CHAPTER 3 ARITHMETIC FOR COMPUTERS
CHAPTER 4 ASSESSING AND UNDERSTANDING PERFORMANCE OF CPU
CHAPTER 5 THE PROCESSOR: DATA PATH AND CONTROL-1
THE PROCESSOR: DATA PATH AND CONTROL-2
CHAPTER 7 LARGE AND FAST: EXPLOITING MEMORY HIERARCHY-P1
LARGE AND FAST: EXPLOITING MEMORY HIERARCHY-P2
CHAPTER 6 ENHANCING CPU PERFORMANCE WITH PIPELINING WITH CONCEPT OF CHAPTER 5
CHAPTER 8 STORAGE, NETWORKS, AND OTHER PERIPHERALS |
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課程目標 |
1.BASIC CONCEPT OF RISC (REDUCED INSTRUCTION SET COMPUTER), COMPARED WITH CISC (COMPLEX INSTRUCTION SET COMPUTER)
2.THE ASSEMBLY/MACHINE LANGUAGE OF THE MIPS CPU
3.DETAILED CPU DESIGN:
INSTRUCTION SET
DATA PATH
CONTROL UNIT
ARITHMETIC LOGIC UNIT (ALU)
TECHNIQUES TO ENHANCE CPU PERFORMANCE, E.G., PIPELINING.
4.MEMORY HIERARCHY:
CACHE: HOW TO IMPROVE DATA/INSTRUCTION ACCESS TIME?
VIRTUAL MEMORY: HOW TO HANDLE PROGRAM/DATA THAT IS LARGER THAN YOUR PHYSICAL (MAIN) MEMORY?
5.I/O PERIPHERALS:
KNOW MORE ABOUT I/O DEVICES.
HOW TO TRANSFER DATA DIRECTLY FROM I/O DEVICES TO MEMORY? LEARN THE TECHNIQUE OF DIRECT MEMORY ACCESS (DMA).
WHAT IS THE RELATIONSHIP AMONG CPU/MEMORY/I-O? |
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課程要求 |
PREREQUISITE:
SWITCH CIRCUITS AND LOGIC DESIGNS
ELECTRONICS |
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預期每週課後學習時數 |
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Office Hours |
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指定閱讀 |
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參考書目 |
TEXTBOOK: (MAIN) “COMPUTER ORGANIZATION AND DESIGN: THE HARDWARE/SOFTWARE INTERFACE”, BY DAVID A. PATTERSON AND JOHN L. HENNESSY, 2004, 3RD EDITION (新月, 東華).
REFERENCE: (VERILOG CODING, OPTIONAL)“ADVANCED DIGITAL DESIGN WITH THE VERILOG HDL,” BY M. D. CILETTI, PRENTICE HALL, 2003.
(VERILOG CODING, OPTIONAL)“VERILOG HDL: A GUIDE TO DIGITAL DESIGN AND SYNTHESIS,” 2ND ED., BY SAMIR PALNITKAR, SUNSOFT PRESS, 2003 (全華)
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評量方式
(僅供參考) |
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